Explore documented scientific discoveries, original research and new scientific developments. Search the library by topic, category or date.
arXiv:2611.03400v1 Announce Type: new Abstract: Read mapping algorithms represent a critical bottleneck in genomic analysis pipelines due to the resources required; a problem that is becoming more pronounced as sequencing technologies advance and datasets expand.
arXiv Computer Science ARRead article →arXiv:2611.03392v1 Announce Type: new Abstract: Neural network inference at the edge must fit tight energy budgets. Existing benchmarks compare few devices, do not report energy on a common basis, and omit the newest microcontrollers with an NPU or the 1 GHz Cortex-M85. Hardware-aware design also ranks networks by MAC count, yet no study has tested whether this proxy holds across accelerators.
arXiv Computer Science ARRead article →arXiv:2611.03173v1 Announce Type: new Abstract: Large Mixture-of-Experts (MoE) models are promising for local inference because sparse routing allows the routed-expert pool to reside on SSD while DRAM caches recently used experts. However, under practical DRAM cache capacities, substantial SSD I/O remains on the critical path despite I/O-computation overlap.
arXiv Computer Science ARRead article →arXiv:2611.02974v1 Announce Type: new Abstract: In FPGA soft processors with shared backing block RAM, memory admission can stall a multiplication after its product has been prepared. We study how admission timing changes result retention in PaceRV, our board-tested five-stage RV32IMC core, using fixed binaries and matched dynamic instructions.
arXiv Computer Science ARRead article →arXiv:2611.02520v1 Announce Type: new Abstract: Kinetic molecular memristors offer a compelling path toward high-density analog in-memory computing by achieving 14-bit precision, wherein discrete redox transitions and counterion displacements dictate non-volatile conductance across a deterministic energy landscape.
arXiv Computer Science ARRead article →arXiv:2611.02401v1 Announce Type: new Abstract: Autoregressive decoding of large language models (LLMs) on edge devices is dominated by memory-bound general matrix--vector multiplication (GeMV) operations. Processing-using-DRAM (PUD) is a promising computing paradigm that can alleviate this bottleneck by reducing processor--memory data transfers and enabling massively parallel computation within DRAM (e.g., across…
arXiv Computer Science ARRead article →arXiv:2611.02365v1 Announce Type: new Abstract: Depth-guided, cost-volume-based Generalizable 3D Gaussian Splatting (G-3DGS) encoders reconstruct scenes as sets of Gaussian primitives directly from multi-view images without requiring per-scene optimization, thereby facilitating feed-forward novel-view synthesis on edge computing platforms. However, their shared encoder architecture presents two primary bottlenecks.
arXiv Computer Science ARRead article →arXiv:2611.02023v1 Announce Type: new Abstract: Modern FPGA SoCs are no longer just collections of accelerators on top of a programmable fabric. They combine programmable logic with hardened processors, NoCs, and components that dominate end-to-end performance. Evaluating individual pieces is insufficient; system performance depends on the interplay of SoC components.
arXiv Computer Science ARRead article →arXiv:2611.01904v1 Announce Type: new Abstract: To sustain the computational demands of modern ML and HPC workloads, programmable accelerators integrate large arrays of processing elements (PEs), typically built around single-issue in-order cores to maximize integration density and energy efficiency.
arXiv Computer Science ARRead article →arXiv:2611.01707v1 Announce Type: new Abstract: Analog In-Memory Computing (IMC) is a promising paradigm for accelerating GEMM-based AI workloads by executing computations directly within the memory array in the analog domain. While IMC delivers substantial energy and throughput improvements, it can suffer from significant task accuracy degradation due to analog-to-digital converter (ADC) quantization noise, which…
arXiv Computer Science ARRead article →arXiv:2611.01611v1 Announce Type: new Abstract: Spiking Neural Networks (SNNs) provide an event-driven paradigm for energy-efficient edge computing. However, operation-level sparsity in SNNs does not necessarily eliminate the hardware costs associated with redundant output neurons, including neuron-state maintenance, partial-sum (psum) accesses, and on-chip storage requirements.
arXiv Computer Science ARRead article →arXiv:2611.01598v1 Announce Type: new Abstract: Heterogeneous embedded boards pair a Linux application processor with a real-time microcontroller (MCU), which suggests moving a task between the two domains when its timing degrades. We present QFabric, a prototype that treats cross-domain placement as guarded recovery from a violated empirical soft real-time contract: a bounded task is compiled for both domains…
arXiv Computer Science ARRead article →arXiv:2611.01473v1 Announce Type: new Abstract: Clock meshes are widely used in high-performance VLSI systems to minimize skew and tolerate On-Chip Variation (OCV) in nanometer technologies. However, analyzing meshes is difficult because reconvergent paths and multi-source drivers prevent static timing analysis (STA) tools from handling mesh loops, making SPICE the industrial standard.
arXiv Computer Science ARRead article →arXiv:2611.00915v1 Announce Type: new Abstract: Low-bit quantization reduces the data movement and computation costs of large language model (LLM) inference, but uniform widths can waste precision and degrade model quality. Existing mixed-precision methods do not fully account for how the other input of the current GEMM tile affects output error when selecting one input's width.
arXiv Computer Science ARRead article →arXiv:2611.00669v1 Announce Type: new Abstract: Deep learning (DL) models for real-time wearable sleep staging often rely on long-kernel temporal convolutions, a requirement that current accelerators struggle to support efficiently. To overcome this, we present an FPGA-based CNN-BiLSTM accelerator that incorporates several algorithm-hardware co-design techniques to enable efficient edge inference.
arXiv Computer Science ARRead article →arXiv:2611.00660v1 Announce Type: new Abstract: This letter presents a mixed-precision CNN-LSTM accelerator for EEG-based sleep staging. To efficiently execute long temporal convolutions, a serpentine dataflow propagates activations between neighboring processing elements, reducing memory accesses by 6.2 times and 2.25 times compared with output- and weight-stationary dataflows, respectively.
arXiv Computer Science ARRead article →arXiv:2611.00547v1 Announce Type: new Abstract: The rapid scaling of large language models (LLMs) has unlocked remarkable capabilities across various domains. However, deploying LLMs on mobile devices remains challenging because of their high computational and memory requirements.
arXiv Computer Science ARRead article →arXiv:2611.00487v1 Announce Type: new Abstract: The growing computational demands of deep learning (DL) have driven AI-optimized reconfigurable devices, such as the AMD Versal AI Engines (AIEs), the Intel Stratix 10 NX Tensor Blocks (TBs), and the AMD Ryzen AI NPUs. Their heterogeneous resources and novel dataflow models make efficient exploitation nontrivial, and FPGAs lack native support for structured sparsity.
arXiv Computer Science ARRead article →arXiv:2611.00476v1 Announce Type: new Abstract: Geometric perception on edge must simultaneously achieve two goals that are rarely addressed together: preserve accurate spatial understanding for object localization and operate within stringent latency, memory, energy, and precision constraints.
arXiv Computer Science ARRead article →arXiv:2611.00409v1 Announce Type: new Abstract: This paper proposes an open-source automated LC matching network optimization framework that combines schematic-level design optimization with electromagnetic (EM)-aware post-layout refinement.
arXiv Computer Science ARRead article →arXiv:2611.00292v1 Announce Type: new Abstract: Deep neural network (DNN) accelerators for edge inference must meet tight energy, latency, and area (EDP) constraints, and their optimal hardware architecture and dataflow configuration is typically identified through design space exploration (DSE).
arXiv Computer Science ARRead article →arXiv:2611.00282v1 Announce Type: new Abstract: Randomized caches protect against side-channel attacks by obfuscating the mapping of memory addresses to cache locations. Existing proposals typically describe architectural behavior, leaving practical hardware implementation challenges largely unexplored.
arXiv Computer Science ARRead article →arXiv:2611.00187v1 Announce Type: new Abstract: Large language models (LLMs) are increasingly used to generate analog circuits, yet every netlist must also be verified. We propose LLMs as verification assistants for analog circuits that flag unmet specifications and reliability issues that appear under process, voltage, and temperature (PVT) variation.
arXiv Computer Science ARRead article →arXiv:2611.00117v1 Announce Type: new Abstract: Residual-stream caching can reconstruct transformer key-value (KV) caches losslessly, but its memory advantage depends on architecture. We present AnchorKV, a storage-replay spectrum connecting per-layer residual caching and full recomputation through configurable residual anchors.
arXiv Computer Science ARRead article →