CAPER: Circuit-Aware Parameter-Efficient Reasoning in LLMs for Analog Verification

arXiv:2611.00187v1 Announce Type: new Abstract: Large language models (LLMs) are increasingly used to generate analog circuits, yet every netlist must also be verified. We propose LLMs as verification assistants for analog circuits that flag unmet specifications and reliability issues that appear under process, voltage, and temperature (PVT) variation. These issues emerge from how circuit stages combine, a structure that generic parameter-efficient fine-tuning (PEFT) methods such as LoRA do not capture. To this end, we introduce CAPER, a circuit-aware PEFT method that adds a small branch alongside LoRA to read each stage's properties from the LLM and combine them from the relevant stages.